The invention is directed to an improved approach for implementing prototyping and analysis of electronic circuit designs.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools.
The EDA tools may be used to perform early stage analysis and examinations of an electronic design. For example, the EDA tools may be used to determine whether the electronic design is capable of meeting timing requirements along signal paths in the design. Failure of a design to adequately meet timing requirements could result in an electronic product that may fail under usage and/or not function according to its intended purpose. Therefore, for design and planning purposes, it is very desirable for engineers and designers to be able to obtain an early-stage estimate of the likelihood that a particular design will meet its timing requirements. Early identification of timing problems allows the designer to address the timing identified issues in a much more efficient way than if such timing problems are discovered later in the design cycle.
The problem is that conventional modeling and prototyping techniques causes the prototyping and analysis process to consume an excessive amount of time and computing resources, particularly given the large number of objects and features that exist in modern electronic designs. In addition, conventional modeling and prototyping approaches can fail to identify timing errors at an early stage of the design cycle, such that timing problems are only identified once the analysis has returned to the top level.
As a particular example, consider the process to perform clock tree prototyping of an electronic design. The increasing complexity of modern designs (e.g., Gigascale designs) poses numerous implementation challenges. Given the large number of components such as flip flops in Gigascale designs, one key challenge faced by designers involves accurately planning and implementing the clock tree in the design. The clock tree has a profound effect on the design closure and timing, making it increasingly important to ensure that the process is performed correctly.
One of the main challenges involved in clock tree synthesis for Gigascale designs is processing and system capacity, since early estimation usually involves handling of large amounts of data, which translates into long runtimes and large memory requirements. In conventional approaches, this capacity constraint limits the designer's ability to explore different design possibilities. Another significant challenge pertains to accuracy; with increasing frequencies, the margin of error for the estimates becomes much smaller. At lower process nodes coupling, DFY/DFM (design for yield/design for manufacturing) effects significantly impact routing and indirectly affect timing. In addition, On Chip Variation (OCV) becomes another major challenge, since growing die sizes can cause OCV effects that reduce available time. This effect can be further compounded because of cross partition paths in hierarchical designs.
Therefore, there is a need for an improved approach to implement prototyping and/or modeling for electronic designs that allows for efficient analysis of the electronic designs. There is particularly a need for an improved approach to perform clock tree modeling and prototyping for early-stage analysis of the electronic designs.